This invention an enhances features of an existing FLASH memory, for example the MoSys 1-T eFlash 1 Mbit macro. As known in the art a macro is a design of a complete system or sub-system that can be incorporated into a larger design such as a system on a chip (SOC). A brief description of the key characteristics of the macro implementation and other requirements follows.
FIG. 1 illustrates a prior art FLASH macro 100. The FLASH macro 100 includes a write controller 120, a charge pump 125 and 4 by 32 Kbyte FLASH array blocks 131 to 134. A small amount of the FLASH array is used as configuration data for the device. This is known as ID space and is separate from the user accessible space. FLASH macro 100 requires charge pump 125 to produce voltage higher than a typical power supply voltage needed for write and erase operations. FLASH array blocks 131 to 134 are divided into 16 high voltage banks of 32 rows each containing 16 by 32-bit words in this example. A write operation is performed on a single row. An erase operation is performed concurrently on 8 rows. Each of the 4 FLASH blocks 131 to 134 includes a corresponding sense-amplifier structure 135 to 138 for reads. Sense-amplifier structures 135 to 138 are connected write controller 120 permitting verification that programmed values are fully written. Each of the 4 FLASH blocks 131 to 134 has a corresponding error correction code circuit 141, 142, 143 and 144. Data stored in FLASH macro 100 may be accessed by bus 110.